A Specially Designed Transient Faults Injection Technique at the Vhdl Level and Modeling

This paper presents a technique to improve verification at VHDL level by a specially designed transient faults injection block. By this technique fault insertion time, can be randomized. A probabilistic model of faulty periods, the time period where at least one fault exists and a fault analysis to derive the optimum faulty period is presented. Distribution functions are derived to represent the case of false alarm, where a transient fault is flagged as permanent, and the case of a miss, where too many faults coexist thus overcoming the checker‟s capability to detect them. These derivations are compared with the results of a simulation program representing the model. The VHDL coding utilized the Xilinx ISE 11.1, and the simulation has been performed in ISim simulator.